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52 21555 Non-Transparent PCI-to-PCI Bridge User Manual
PCI Bus Transactions
When any of these conditions is not met, the 21555 uses the memory write command. When a subsequent cache
line in the transaction does not have all bytes enabled, the 21555 terminates the MWI transaction and delivers the
remaining data using a memory write command.
The 21555 continues the MWI transaction as long as a full cache line is posted in the posted write queue. A a full
cache line corresponds to the cache line size of the target bus. When the 21555 is within one data phase of
delivering a complete cache line and there is not another full cache line posted in the queues, the 21555 master
terminates the transaction at the cache line boundary. For example: 1 Dword for 32-bit transactions or 2 Dwords for
64-bit transactions. This can occur because:
• The transaction has terminated on the initiator bus at a non-cache line boundary.
• The write data is being pulled from the queue faster than it is being posted. In this, a full cache line is not
posted soon enough to continue the MWI.
When the 21555 terminates an MWI transaction before all write data is delivered, it initiates another write
transaction to finish delivery of the write data. When a fraction of a cache line remains, the 21555 initiates the
transaction with the memory write command. When at least a complete cache line was subsequently posted, then
the 21555 once again initiates the transaction with an MWI command.
5.2.3 64-bit Extension Posted Write Transaction
The 21555 uses the 64-bit extension signals, when implemented, for accepting and delivering posted write data.
As a target, the 21555 asserts ACK64# in response to the initiator’s assertion of REQ64# for memory writes and
MWI commands if the address is Quadword aligned (address bit AD[2] is zero). The 21555 then accepts 64 bits of
data per data phase without inserting target wait states.
As an initiator, the 21555 asserts REQ64# when delivering posted write data as long as the burst consists of a
minimum of 4 Dwords, and the original address is Quadword (64-bit) aligned. When the target asserts ACK64#,
write data is delivered 64 bits per data phase without inserting master wait states. When the burst ends on an odd
Dword address boundary, the 21555 forces the high four byte enables of the last data phase in the burst to be
deasserted.
5.2.4 Write Performance Tuning Options
The 21555 implements several features and options that affect write performance when forwarding posted write
transactions
5.2.4.1 Memory Write and Invalidate
When the MWI Enable bit in configuration space is set for that corresponding interface, the 21555 is enabled to
initiate MWI transactions as described in Section 5.2.2.
5.2.4.2 Fast Back-to-Back
The 21555 may be enabled to initiate fast back-to-back transactions. The 21555 must have the bus grant the clock
cycle before it asserts FRAME# for the second transaction, and the Fast Back-to-Back Enable bit must be set for
the interface on which the 21555 is initiating the transaction. When both of these conditions exist, the 21555 may
initiate the second transaction with fast back-to-back timing following a write transaction that is not terminated
with STOP#.