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56 21555 Non-Transparent PCI-to-PCI Bridge User Manual
PCI Bus Transactions
The 21555 requests the target bus and initiates the delayed read transaction as soon as the 21555 ordering rules
allow. See Section 5.7. When the transaction is a nonprefetchable read as described in Section 5.4.1, the 21555
requests only a single Dword of data. When the transaction is a memory read, the 21555 follows the prefetch rules
outlined in Section 5.4.2. The 21555 completes the transaction on the target bus and adds the read data and parity to
the read data queue and the completion status to the delayed transaction queue. This phase of the delayed
transaction is called the Delayed Read Completion (DRC). When the 21555 receives 2
24
consecutive target retries
from the target, the 21555 discards the delayed read transaction and conditionally asserts SERR# on the initiator
bus. See Chapter 12. This retry counter may be disabled by setting the Retry Counter Disable bit in the Chip
Control 0 Configuration register. If the transaction is discarded before completion, the 21555 returns a target abort
to the initiator.
When the initiator repeats the transaction using the same address, bus command, and byte enables, then the 21555
returns the read data, parity, and appropriate target termination when ordering rules allow. For all memory read type
transactions, the 21555 aliases the memory read, memory read line, and memory read multiple commands when
comparing a transaction in the delayed transaction queue to one initiated on the PCI bus. Regardless of the exact
command used, when the address matches and both commands are any type of memory read, the 21555 considers it
a match. When there is no match, the 21555 is discarding data. When the ordering rules prevent returning the
completion at that point, the 21555 returns target retry. The target terminations are listed in Table 14.
When the 21555 has a delayed completion to return to an initiator, and the initiator does not repeat the transaction
before the Master Time-out Counter for that interface expires, then the 21555 discards the delayed completion
transaction. When enabled to do so, the 21555 asserts SERR# on the initiator bus. The Master Time-out Counter
expiration value is either 2
10
or 2
15
PCI clock cycles, programmable in the Chip Control 0 configuration register.
The Master Time-out Counter is disabled when the Master Time-out Disable bit in the Chip Control 0 configuration
register is zero.
5.4.1 Nonprefetchable Reads
The following transactions are considered by the 21555 to be nonprefetchable:
• I/O transactions.
• Configuration transactions.
• Transactions using the memory read command that address a range configured as nonprefetchable.
• Primary bus memory reads to the Expansion ROM BAR.
When initiating a nonprefetchable read, the 21555 requests only a single Dword of read data from the target. The
21555 uses the same byte enables driven by the initiator of the transaction.
When the 21555 returns the read data to the initiator, it asserts STOP# with TRDY# when the initiator is requesting
multiple Dwords.
Table 14. Delayed Read Transaction Target Termination Returns
Target Bus Response Initiator Bus Response
TRDY# TRDY# and STOP# when returning last data and FRAME# is asserted
Target abort Target abort
Master abort
TRDY# and FFFFFFFFh when Master Abort Mode bit = 0.
Target abort when Master Abort Mode bit = 1.