Filter
Top Products
21555 Non-Transparent PCI-to-PCI Bridge User Manual 15
Introduction 2
The Intel
®
21555 is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O
applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-MHz capability. In this
document the 21555 non-transparent device is compared to the related 21154 transparent devices. Both devices
have similar operating characteristic.
The 21555 is a “non-transparent” PCI-to-PCI Bridge (PPB) that acts as a gateway to an intelligent subsystem. It
allows a local processor to independently configure and control the local subsystem. The 21555 implements an I20
message unit that enables any local processor to function as an intelligent I/O processor (IOP) in an I20-capable
system. Since the 21555 is architecture independent, it works with any host and local processors that support a PCI
bus. This architecture independence enables vendors to leverage existing investments while moving products to
PCI technology.
Unlike a transparent PPB, the 21555 is specifically designed to bridge between two processor domains. The
processor domain on the primary interface of the 21555 is referred to as the host domain, and its processor is the
host processor. The secondary bus interfaces to the local domain and the local processor. Special features include
support of:
• Independent primary and secondary PCI clocks. See Chapter 7.
• Independent primary and secondary address spaces.
• Address translation between the primary (host) and secondary (local) domains. See Chapter 4.
The 21555 allows add-in card vendors to present a higher level of abstraction to the host system than is possible
with a transparent PPB. The 21555 uses a Type 0 configuration header, which presents the entire subsystem as a
single “device” to the host processor. This allows loading of a single device driver for the entire subsystem, and
independent local processor initialization and control of the subsystem devices. Since the 21555 uses a Type 0
configuration header, it does not require hierarchical PPB configuration code.
The 21555 forwards transactions between the primary and secondary PCI buses as does a transparent PPB. In
contrast to a transparent PPB, the 21555 can translate the address of a forwarded transaction from a system address
to a local address, or vice versa. This mechanism allows the 21555 to hide subsystem resources from the host
processor and to resolve any resource conflicts that may exist between the host and local subsystems.
The 21555 operates at 3.3 V, but is also 5.0-V I/O tolerant. Adapter cards designed for the 21555 can be keyed as a
PCI universal card edge connector, permitting use in either a 5-V or 3-V slot.
2.1 Comparing a 21555 to a Transparent PPB
The 21555 is functionally similar to a transparent PPB in that both provide a connection path between devices
attached to two independent PCI buses. A 21555 and a PPB allow the electrical loading of devices on one PCI bus
to be isolated from the other bus while permitting concurrent operation on both buses. Since the PCI Local Bus
Specification restricts PCI option cards to a single electrical load, the ability of PPBs and the 21555 to spawn PCI
buses enables the design of multi-device PCI option cards. The key difference between a PPB and the 21555 is that
the presence of a PPB in a connection path between the host processor and a device is transparent to devices and
device drivers, while the presence of the 21555 is not. This difference enables the 21555 to provide features that
better support the use of intelligent controllers in the subsystem.