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21555 Non-Transparent PCI-to-PCI Bridge User Manual 59
PCI Bus Transactions
5.4.4.3 Read Queue Full Threshold Tuning
The 21555 implements read queue management control bits for each read data queue in the Chip Control 1
configuration register. These bits specify at what read-queue threshold the 21555 initiates a delayed prefetchable
read transaction on the target bus. Use of these bits can minimize fragmentation of prefetchable read bursts. The
encoding and behavior of these bits are as follows:
• 00b: at least eight Dwords free in read data queue for all memory read commands.
• 01b: at least eight Dwords free for all memory read commands (same as 00b).
• 10b: at least one cache line free for MRL and MRM, eight Dwords free for memory read.
• 11b: at least one cache line free for all memory read commands .
In these cases, the initiator bus cache line size is used. When the cache line size is not set to a valid value, 8 Dwords
is used for the read queue threshold.
For non-prefetchable memory reads, a threshold of 8 Dwords (one read queue block) is always used.
5.5 64-Bit and 32-Bit Transactions Initiated by the 21555
The 21555 requests a 64-bit transaction on the primary or secondary bus 64-bit PCI extension by asserting
p_req64_l on the primary bus or s_req64_l on the secondary bus, respectively, during the address phase.
The 21555 asserts and deasserts REQ64# during the same cycles in which it asserts and deasserts FRAME#,
respectively.
Under the following specific circumstances, the 21555 does not use the 64-bit extension when initiating
transactions and therefore does not assert REQ64#:
• Signal p_req64_l was not asserted by the primary bus central function during reset for upstream transactions
only. The 64-bit extension is not supported on primary PCI bus.
• The 21555 is initiating an I/O transaction.
• The 21555 is initiating a configuration transaction.
• The 21555 is initiating a nonprefetchable memory read transaction.
• The 21555 is initiating a special cycle transaction.
• The address is not Quadword aligned (AD[2] = 1).
• 3 Dwords or less in posted right buffer.
• The 21555 is resuming a memory write transaction after a target disconnect, and ACK64# was not asserted by
the target in the previous transaction. (This does not apply when the previous target termination was a target
retry.)
• A single Dword read transaction is being performed.
• The address is near the top of a cache line (AD[3] = 1) applies to prefetchable read transactions.