Intel 21555 Network Router User Manual


 
21555 Non-Transparent PCI-to-PCI Bridge User Manual 205
Acronyms A
1D One-dimensional
2D Two-dimensional
AGP Accelerated Graphics Port
ANSI American National Standards Institute
API Application Programming Interface
BAR Base Address Register
BiST Built-In Self-Test
CLS Cache Line Sizes
CSR Control and Status Registers
DAC Dual Address Cycle
DRC Delayed Read Completion
DRR Delayed Read Request
DWC Delayed Write Completion
DWR Delayed Write Request
ETSI European Telecommunications Standards Institute
FFT Fast Fourier transform
FIR Finite impulse response
Flash Nonvolatile memory
GOB Group of blocks
GPIO General Purpose Input Output
I20 Intelligent Input/Output
IDCT Inverse discrete cosine transform
IEC International Electrotechnical Commission
IIR Infinite impulse response
IOP Input Output Processor
IPP Integrated Performance Primitives
ISO International Standards Organization
ITU International Telecommunication Union
IXA Internet Exchange Architecture; for example: Intel® IXA.
LMS Least mean square
MB Macroblock
MC Motion compensation