198 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Primary Lockout bit
action before clearing the 130
power management 71
with serial Preload 69
with SROM operation 69, 70
Primary lockout bit
type 0 access 44
Processor
domains 15
processor 15
Q
Queue empty condition 50
R
Read and write access
Y, N, Primary, Secondary, Special Cases 121
Read flow-through 57
Read performance features and tuning options 57
Read queue full threshold tuning 59
Registers
Configuration CSR 143
Configuration Own Bits Register 142
Downstream and Upstream Configuration Address Reg-
isters 141
Downstream Configuration Data and Upstream Configu-
ration Data Registers 142
Downstream I/O Address and Upstream I/O Address
Registers 144
Downstream I/O Data and Upstream I/O Data Registers
145
Downstream I/O or Memory 1 and Upstream I/O or
Memory 0 BAR 133
Downstream I/O or Memory 1 and Upstream I/O or
Memory 0 Setup Registers 138
Downstream I/O or Memory 1 and Upstream I/O or
Memory 0 Translated Base Register 136
Downstream Memory 0, 2, 3, and Upstream Memory 1
Setup Registers (Sheet 1 of 2) 139
Downstream Memory 0, 2, 3, and Upstream Memory 1
Translated Base Register 137
Downstream Memory 2 and 3 BAR, and Upstream Mem-
ory 1 BAR 134
I/O Control and Status Register 146
I/O Own Bits Registers 145
JATAG boundary-Scan Register 191
JATAG bypass Register 191
Lookup Table Data Register 147
Lookup Table Offset Register 146
Primary and Secondary CSR I/O BARs 132
Primary CSR and Downstream Memory 0 BAR 130
Secondary CSR Memory BARs 132
Secondary interrupt pin register 155
Upper 32 Bits Downstream Memory 3 Bar 135
Upper 32 Bits Downstream Memory 3 Setup Register
140
Upstream Memory 2 Bar 135
Upstream Memory 2 Lookup Table 147
S
Secondary interrupt pin register 155
T
Transparent versus non-transparent
an overview of 15
Type 0 configuration header 15
U
Upstream base address register 34
Use of interrupt mask bits 101
Use of interrupt request status bits 101
V
Vendor ID 122
Voltage
operating 15
W
Write performance tuning options
Write flow-through 53