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21555 Non-Transparent PCI-to-PCI Bridge User Manual 185
List of Registers
16.13 Init Registers
This section describes the Power management, Reset, and Hot-swap registers. See Chapter 2 for theory of operation
information.
1
Upstream Delayed
Read Transaction
Discarded
R/W
Disables s_serr_l assertion when the 21555 discards an upstream
delayed read transaction request after receiving 2
24
target retries
from the primary bus target.
Reset value is 0
2
Upstream Delayed
Write Transaction
Discarded
R/W
Disables s_serr_l assertion when the 21555 discards an upstream
delayed write transaction request after receiving 2
24
target retries
from the primary bus target.
Reset value is 0
3
Upstream Posted
Write Data Discarded
R/W
Disables s_serr_l assertion when the 21555 discards an upstream
posted write transaction after receiving 2
24
target retries from the
primary bus target.
Reset value is 0
4
Target Abort during
Upstream Posted
Write
R/W
Disables s_serr_l assertion when the 21555 detects a target abort
on the primary interface in response to an upstream posted write.
Reset value is 0
5
Master Abort during
Upstream Posted
Write
R/W
Disables s_serr_l assertion when the 21555 detects a master abort
on the primary interface when initiating an upstream posted write.
Reset value is 0
6
Upstream Posted
Write Parity Error
R/W
Disables s_serr_l assertion when the 21555 detects p_perr_l
asserted during an upstream posted write.
Reset value is 0
7 Reserved R Reserved. Returns 0 when read.
Table 118. Power Management ECP ID and Next Pointer Register
• Primary byte offset: DD:DCh
• Secondary byte offset: DD:DCh
Bit Name R/W Description
7:0 PM ECP ID R
Power Management Enhanced Capabilities Port ID. Read only as 01h to identify
these ECP registers as Power Management registers.
15:8 PM Next Ptr R
Pointer to next ECP registers. Reads as E4 to indicate the first register of the
next set of ECP registers, which support Vital Product Data, and resides at offset
E4h.
Table 117. Secondary SERR# Disable Register