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Epson Research and Development Page 7
Vancouver Design Center
Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
List of Figures
Figure 3-1: Typical System Diagram (SH-4 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 3-2: Typical System Diagram (SH-3 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 3-3: Typical System Diagram (M68K #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3-4: Typical System Diagram (M68K #2 Bus) . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3-5: Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus). . . . . . . . . . . . . . . . .14
Figure 4-1: System Block Diagram Showing Data Paths. . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5-1: Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 7-2: SH-3 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 7-3: MC68K #1 Bus Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 7-4: MC68K #2 Timing (MC68030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 7-5: Generic #1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 7-6: Generic #2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 7-7: Clock Input Requirements for CLKI . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 7-8: Clock Input Requirements for BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 7-9: LCD Panel Power On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 7-10: Power Down/Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 7-11: Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 7-12: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .39
Figure 7-13: Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 7-14: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .41
Figure 7-15: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 7-16: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 7-17: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 7-18: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . .45
Figure 7-19: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 7-20: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . .47
Figure 7-21: Dual Monochrome 8-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 7-22: Dual Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . .49
Figure 7-23: Dual Color 8-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 7-24: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 7-25: 12-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 7-26: TFT/D-TFD A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 8-1: Screen-Register Relationship, Split Screen. . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization. . . . . . . . . . . . . . . . .70
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . .71