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Page 22 Epson Research and Development
Vancouver Design Center
S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
5.3 Summary of Configuration Options
5.4 Host Bus Interface Pin Mapping
Table 5-1: Summary of Power On/Reset Options
Configuration
Pin
Power On/Reset State
CNF[3:0]
Select host bus interface as follows:
CNF3 CNF2 CNF1 CNF0 BS# Host Bus
1000X SH-4 interface Big Endian
0000X SH-4 interface Little Endian
1001X SH-3 interface Big Endian
0001X SH-3 interface Little Endian
X010X reserved
1011X MC68K #1, 16-bit Big Endian
0011X reserved
X 1 0 0 X reserved
1101X MC68K #2, 16-bit Big Endian
0101X reserved
X1100 reserved
X1101 reserved
11110 Generic #1, 16-bit Big Endian
01110 Generic #1, 16-bit Little Endian
11111 reserved
01111 Generic #2, 16-bit Little Endian
Table 5-2: Host Bus Interface Pin Mapping
S1D13705
Pin Names
SH-3 SH-4 MC68K #1 MC68K #2 Generic #1 Generic #2
AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]
AB0 A0 A0 LDS# A0 A0 A0
DB[15:0] D[15:0] D[15:0] D[15:0] D[31:16] D[15:0] D[15:0]
WE1# WE1# WE1# UDS# DS# WE1# BHE#
CS# CSn# CSn# External Decode External Decode External Decode External Decode
BCLK CKIO CKIO CLK CLK BCLK BCLK
BS# BS# BS# AS# AS# connect to V
SS
connect to IO V
DD
RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# connect to IO V
DD
RD# RD# RD# connect to IO V
DD
SIZ1 RD0# RD#
WE0# WE0# WE0# connect to IO V
DD
SIZ0 WE0# WE#
WAIT# WAIT# RDY# DTACK# DSACK1# WAIT# WAIT#
RESET# RESET# RESET# RESET# RESET# RESET# RESET#