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Epson Research and Development Page 45
Vancouver Design Center
Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
Figure 7-18: Single Color 8-Bit Panel A.C. Timing (Format 1)
1. Ts = pixel clock period
2. t1
min
= t3
min
- 9Ts
3. t3
min
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
4. t6a
min
= [(REG[08h] bits 4-0) x 8]Ts
5. t6b
min
= [(REG[08h] bits 4-0) x 8 + 2]Ts
6. t7a
min
= [(REG[08h] bits 4-0) x 8 + 11]Ts
7. t7b
min
= [(REG[08h] bits 4-0) x 8 + 11] - t10]Ts
Table 7-14: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol Parameter Min Typ Max Units
t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2 Frame Pulse hold from Line Pulse falling edge 9 Ts
t3 Line Pulse period note 3
t4 Line Pulse pulse width 9 Ts
t6a Shift Pulse falling edge to Line Pulse rising edge note 4
t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5
t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6
t7b Shift Pulse falling edge to Line Pulse falling edge note 7
t8 Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge t14 + 2 Ts
t9 Shift Pulse 2, Shift Pulse period 4 Ts
t10 Shift Pulse 2, Shift Pulse pulse width low 2 Ts
t11 Shift Pulse 2, Shift Pulse pulse width high 2 Ts
t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge 1 Ts
t13 FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge 1 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 25 Ts
Frame Pulse
Line Pulse
Sync Timing
Line Pulse
Shift Pulse 2
FPDAT[7:0]
Data Timing
t14
t1
t2
t3
t4
t8 t9
t10t11
t12 t13
12
t7a
t6b
Shift Pulse
t6a
t7b
t12
t13