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Epson Research and Development Page 7
Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705
Issue Date: 01/02/13 X27A-G-004-02
1 Introduction
This application note describes the hardware required to interface the S1D13705
Embedded Memory LCD Controller and the Toshiba MIPS TMPR3912 Processor. The
pairing of these two devices results in an embedded system offering impressive display
capability with very low power consumption.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
techpubs@erd.epson.com.