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Page 32 Epson Research and Development
Vancouver Design Center
S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.1.5 Generic #1 Interface Timing
Figure 7-5: Generic #1 Timing
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
Table 7-5: Generic #1 Timing
Symbol Parameter Min Max Units
f
BCLK
Bus Clock frequency 50 MHz
T
BCLK
Bus Clock period 1/f
BCLK
MHz
t1
A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1#
low (read cycle)
0ns
t2
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
A[16:0], CS# invalid
0ns
t3 WE0#, WE1# low to D[15:0] valid (write cycle) T
BCLK
t4 RD0#, RD1# low to D[15:0] driven (read cycle) 17 ns
t5 WE0#, WE1# high to D[15:0] invalid (write cycle) 0 ns
t6 D[15:0] valid to WAIT# high (read cycle) 0 ns
t7 RD0#, RD1# high to D[15:0] high impedance (read cycle) 10 ns
t8
WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to
WAIT# driven low
16 ns
t9 BCLK to WAIT# high 16 ns
t10
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
WAIT# high impedance
16 ns
t11 WAIT# high to WE0#, WE1#, RD0#, RD1# high 1T
BCLK
T
BCLK
t8
t5
t9
t3
t1
t10
BCLK
A[16:0]
CS#
WE0#,WE1#
WAIT#
VALID
t2
Hi-Z
Hi-Z
Hi-Z
VALID
t6
t7
VALID
Hi-Z
Hi-Z
D[15:0]
D[15:0]
t4
RD0#, RD1#
(write)
(read)
t11