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Page 48 Epson Research and Development
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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.3.8 Dual Monochrome 8-Bit Panel Timing
Figure 7-21: Dual Monochrome 8-Bit Panel Timing
VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines
HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period = (REG[08h] + 4) x 8Ts
VDP
FPLINE
FPSHIFT
FPDAT[7:0]
FPFRAME
FPLINE
DRDY (MOD)
FPDAT6
1-2 1-6 1-638
FPDAT5
1-3
1-7
1-639
FPDAT4
1-4 1-8
1-640
FPDAT3
241-1 241-5
241-637
FPDAT2
241-638
FPDAT1
241-639
FPDAT0
241-640
FPDAT7
1-1 1-5
1-637
HDP
DRDY (MOD)
241-2 241-6
241-3 241-7
241-4 241-8
VNDP
HNDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242