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Page 8 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the NEC VR4102/VR4111 Microprocessor
X27A-G-008-02 Issue Date: 01/02/13
2 Interfacing to the NEC VR4102/VR4111
2.1 The NEC VR4102/VR4111 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE-based embedded consumer applications in mind, the VR4102/VR4111 offers
a highly integrated solution for portable systems. This section is an overview of the
operation of the CPU bus to establish interface requirements.
2.1.1 Overview
The NEC VR4102/VR4111 is designed around the RISC architecture developed by MIPS.
This microprocessor is designed around the 66MHz VR4100 CPU core which supports 64-
bit processing. The CPU communicates with the Bus Control Unit (BCU) with its internal
SysAD bus. The BCU in turn communicates with external devices with its ADD and DAT
buses that can be dynamically sized to 16 or 32-bit operation.
The NEC VR4102/VR4111 has direct support for an external LCD controller. Specific
control signals are assigned for an external LCD controller that provide an easy interface to
the CPU. A 16M byte block of memory is assigned for the LCD controller with its own chip
select and ready signals available. Word or byte accesses are controlled by the system high
byte signal, SHB#.