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Page 42 Epson Research and Development
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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.3.5 Single Color 4-Bit Panel Timing
Figure 7-15: Single Color 4-Bit Panel Timing
VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines
HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period = (REG[08h] + 4) x 8Ts
VDP
FPLINE
FPDAT[7:4]
LINE1 LINE2 LINE3 LINE4
LINE239 LINE240
FPFRAME
LINE1 LINE2
FPLINE
DRDY (MOD)
FPDAT6
FPDAT5
FPDAT4
FPDAT7
DRDY (MOD)
VNDP
1-R1
1-G1
1-B1
1-R2
1-G2
1-B2
1-R3
1-G3
1-B3
1-R4
1-G4
1-B4
1-B319
1-R320
1-G320
1-B320
HDP
HNDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
FPSHIFT