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Page 16 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
X27A-G-007-04 Issue Date: 01/02/13
3 Interfacing to the MC68EZ328
3.1 The MC68EZ328 System Bus
The MC68EZ328 is Motorola’s second generation Dragonball microprocessor. The
DragonballEZ is an integrated controller for handheld products, based upon the
MC68EC000 microprocessor core. The DragonballEZ differs from its predecessor mainly
in that it has increased speed, a DRAM controller, infrared communication, and an in-
circuit emulator. The bus interface has also been simplified; it implements a 16-bit data bus
and a 24-bit address bus. The bus interface is based on the standard MC68EC000 bus
interface signals although the data bus byte lane control signals of the MC68EC000 bus
interface (UDS
and LDS - upper and lower data strobes) have been replaced by some new
signals intended to simplify the task of interfacing to typical memory and peripheral
devices.
The MC68EC000 bus control signals are well documented in Motorola’s user manuals, and
will not be described here. A brief summary of the new signals appears below:
• Output Enable (OE
) is asserted when a read cycle is in process; it is intended to connect
to the output enable control of a typical static RAM, EPROM, or Flash EPROM device.
• Upper Write Enable and Lower Write Enable (UWE
/ LWE) are asserted during
memory write cycles for the upper and lower bytes of the 16-bit data bus; they may be
directly connected to the write enable inputs of a typical memory device.
The S1D13705 implements the MC68000 bus interface using its MC68K #1 mode but this
mode requires the MC68EC000 control signals UDS
and LDS so this mode cannot be used
to connect the MC68EZ328 directly to the S1D13705. However, the Generic #1 interface
mode on the S1D13705 is well suited to interface to the MC68EZ328.
3.2 Chip-Select Module
The MC68EZ328 can generate up to 8 chip select outputs, organized into four groups “A”
through “D”.
Each chip select group has a common base address register and address mask register, to
set the base address and block size of the entire group. In addition, each chip select within
a group has its own address compare and address mask register, to activate the chip select
for a subset of the group’s address block. Finally, each chip select may be individually
programmed to control an 8 or 16-bit device, and each may be individually programmed to
generate from 0 through 6 wait states internally, or allow the memory or allow the memory
or peripheral device to terminate the cycle externally through use of the standard MC68000
DTACK
signal.
Groups A and B are used to control ROM, SRAM, and Flash memory devices and have a
block size of 128K bytes to 16M bytes. Chip select A0 is active immediately after reset and
is a global chip-select so it is typically used to control a boot EPROM device. This chip