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Page 18 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Philips MIPS PR31500/PR31700 Processor
X27A-G-012-02 Issue Date: 01/02/13
5.4 S1D13705 Configuration
The S1D13705 is configured at power up by latching the state of the CNF[3:0] pins. Pin
BS# also plays a role in host bus interface configuration. For details on configuration, refer
to the S1D13705 Hardware Functional Specification, document number X27A-A-001-xx.
The table below shows those configuration settings relevant to this specific interface.
Table 5-2: S1D13705 Configuration Using the IT8368E
S1D13705
Configuration
Pin
Value hard wired on this pin is used to configure:
1 (IO V
DD
)0 (V
SS
)
BS# Generic #2
Generic #1
CNF3 Big Endian
Little Endian
CNF[2:0]
111: Generic #1 or #2
= configuration for connection using ITE IT8368E