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Page 14 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the NEC VR4181A™ Microprocessor
X27A-G-013-02 Issue Date: 01/02/13
4.3 NEC VR4181A Configuration
The NEC VR4181A must be configured through its internal registers in order to map the
S1D13705 to the external LCD controller space. The following register values must be set.
Register LCDGPMD at address 0B00 032Eh must be set as follows.
• Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD
controller interface. This also maps pin SHCLK to #LCDCS and pin LOCLK to
#MEMCS16.
• Bits [1:0] must be set to 01b to reserve 128Kbytes of memory address range
133E 0000h to 133F FFFFh for the external LCD controller.
Register GPMD2REG at address 0B00 0304h must be set as follows.
• Bits [9:8] (GP20MD[1:0]) must be set to 11b to map pin GPIO20 to #UBE.
• Bits [5:4] (GP18MD[1:0]) must be set to 01b to map pin GPIO18 to IORDY.