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Epson Research and Development Page 11
Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705
Issue Date: 01/02/13 X27A-G-004-02
3.3 Generic #2 Interface Mode
Generic #2 interface mode is a general and non-processor-specific interface mode on the
S1D13705. The Generic # 2 interface mode was chosen for this interface due to the
simplicity of its timing and compatibility with the TMPR3912 control signals.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
S1D13705. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
register and memory address space.
• WE1# is the high byte enable for both read and write cycles for the S1D13705, to be
driven low when the host CPU accesses the S1D13705.
• WE0# is the write enable for the S1D13705, to be driven low when the host CPU is
reading data from the S1D13705.
• RD# is the read enable for the S1D13705, to be driven low when the host CPU is
reading data from the S1D13705.
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the S1D13705 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 13705 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
face for Generic #2 mode. However, BS# is used to configure the S1D13705 for
Generic #2 mode and should be tied high (connected to IO V
DD
). RD/WR# should also
be tied high.