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Epson Research and Development Page 35
Vancouver Design Center
Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
Figure 7-8: Clock Input Requirements for BCLK
Table 7-8: Clock Input Requirements for BCLK
Symbol Parameter Min Max Units
f
BCLK
Input Clock Frequency (BCLK) 50 MHz
T
BCLK
Input Clock period (BCLK) 1/f
CLKI
t
PWH
Input Clock Pulse Width High (BCLK) 8 ns
t
PWL
Input Clock Pulse Width Low (BCLK) 8 ns
t
f
Input Clock Fall Time (10% - 90%) 5 ns
t
r
Input Clock Rise Time (10% - 90%) 5 ns
t
PWL
t
PWH
t
f
Clock Input Waveform
t
r
T
BCLK
V
IH
V
IL
10%
90%