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Page 8 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
X27A-G-007-04 Issue Date: 01/02/13
2 Interfacing to the MC68328
2.1 The MC68328 System Bus
The MC68328 is the first generation of Motorola’s Dragonball microprocessors. The
MC68328 is an integrated controller for handheld products, based upon the MC68EC000
microprocessor core. It implements a 16-bit data bus and a 32-bit address bus. The bus
interface consists of all the standard MC68EC000 bus interface signals, plus some new
signals intended to simplify the task of interfacing to typical memory and peripheral
devices.
The MC68EC000 bus control signals are well documented in Motorola’s user manuals, and
will not be described here. A brief summary of the new signals appears below:
• Output Enable (OE
) is asserted when a read cycle is in process; it is intended to connect
to the output enable control of a typical static RAM, EPROM, or Flash EPROM device.
• Upper Write Enable and Lower Write Enable (UWE
/ LWE) are asserted during
memory write cycles for the upper and lower bytes of the 16-bit data bus; they may be
directly connected to the write enable inputs of a typical memory device.
The S1D13705 implements the MC68EC000 bus interface using its MC68K #1 mode, so
this mode may be used to connect the MC68328 directly to the S1D13705 with no glue
logic. However, several of the MC68EC000 bus control signals are multiplexed with IO
and interrupt signals on the MC68328, and in many applications it may be desirable to
make these pins available for these alternate functions. This requirement may be accommo-
dated through the use of the Generic #1 interface mode on the S1D13705.
2.2 Chip-Select Module
The MC68328 can generate up to 16 chip select outputs, organized into four groups, “A”
through “D”.
Each chip select group has a common base address register and address mask register, to
set the base address and block size of the entire group. In addition, each chip select within
a group has its own address compare and address mask register, to activate the chip select
for a subset of the group’s address block. Finally, each chip select may be individually
programmed to control an 8 or 16-bit device, and each may be individually programmed to
generate from 0 through 6 wait states internally, or allow the memory or peripheral device
to terminate the cycle externally through use of the standard MC68000 DTACK
signal.
Groups A and B can have a minimum block size of 64K bytes, so these are typically used
to control memory devices. Chip select A0 is active immediately after reset, so it is
typically used to control a boot EPROM device. Groups C and D have a minimum block
size of 4K bytes, so they are well-suited to controlling peripheral devices. Chip select D3
is associated with the MC68328 on-chip PCMCIA control logic.