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Epson Research and Development Page 9
Vancouver Design Center
Interfacing to an 8-bit Processor S1D13705
Issue Date: 01/12/20 X27A-G-015-01
3 S1D13705 Bus Interface
This section is a summary of the host bus interface modes available on the S1D13705 and
offers some detail on the Generic #2 Host Bus Interface used to implement the interface to
an 8-bit processor.
The S1D13705 provides a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. The bus interface mode used in this example is:
• Generic #2 (this bus interface is ISA-like and can easily be modified to support an 8-bit
CPU).
3.1 Host Bus Pin Connection
The following table shows the functions of each host bus interface signal.
Note
If the CPU does not have address A16 all 80K Bytes of embedded memory will not be
accessible.
For details on configuration, refer to the S1D13705 Hardware Functional Specification,
document number X27A-A-001-xx.
Table 3-1: Host Bus Interface Pin Mapping
S1D13705
Pin Names
Generic #2 Description
AB[16:1] A[16:1] Address [16:1]
AB0 A0 Address A0
DB[15:0] D[15:0] Data
WE1# BHE# Byte High Enable
CS# External Decode Chip Select
BCLK BCLK Bus Clock
BS# n/c Must be tied to IO V
DD
RD/WR# n/c Must be tied to IO V
DD
RD# RD# Read
WE0# WE# Write
WAIT# WAIT#
RESET# RESET#