Filter
Top Products
Epson Research and Development Page 21
Vancouver Design Center
S5U13705B00C Rev. 2.0 Evaluation Board User Manual S1D13705
Issue Date: 2002/09/16 X27A-G-014-02
6.8 Clock Options
The input clock (CLKI) frequency can be up to 50MHz for the S1D13705 if the internal
divide-by-2 mode is set. If the clock divider is not used, the maximum CLKI frequency is
25MHz. There is no minimum input clock frequency.
A 6.0MHz oscillator (U2, socketed) is provided as the input clock source. However,
depending on the LCD resolution, desired frame rate and power consumption budget,
another clock frequency may be required.
A jumper, JP7 is provided to allow CLKI input to be the same as BCLK input, for systems
in which is desired to use only one clock signal for both BCLK and CLKI.
The bus clock (BCLK) is selectable and can be provided by a 50MHz oscillator (U7,
socketed) or the host CPU (for non-PCI host).