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Page 38 Epson Research and Development
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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.3.3 Single Monochrome 4-Bit Panel Timing
Figure 7-11: Single Monochrome 4-Bit Panel Timing
VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines
HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period = (REG[08h] + 4) x 8Ts
VDP
FPLINE
FPSHIFT
LINE1 LINE2 LINE3 LINE4 LINE239 LINE240
FPFRAME
LINE1 LINE2
FPLINE
DRDY (MOD)
1-2 1-6 1-318
1-3
1-7
1-319
1-4 1-8
1-320
1-1 1-5
1-317
DRDY (MOD)
VNDP
HDP HNDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
FPDAT[7:4]]
FPDAT6
FPDAT5
FPDAT4
FPDAT7
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1