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Epson Research and Development Page 21
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor S1D13705
Issue Date: 01/02/13 X27A-G-010-02
This code was entered into the memory of the MPC821ADS using the line-by-line
assembler in MPC8BUG, the debugger provided with the ADS board. It was executed on
the ADS and a logic analyzer was used to verify operation of the interface hardware.
Note
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
It is important to note that when the MPC821 comes out of reset, its on-chip caches and
MMU are disabled. If the data cache is enabled, then the MMU must be set up so that the
S1D13705 memory block is tagged as non-cacheable, to ensure that accesses to the
S1D13705 will occur in proper order, and also to ensure that the MPC821 does not attempt
to cache any data read from or written to the S1D13705 or its display buffer.