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Intel
®
IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
The Intel
®
IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps
applications. The IXF1104 supports a System Packet Interface Phase 3 (SPI3) system interface
to a network processor or ASIC, and concurrently supports copper and fiber physical layer
devices (PHYs).
The copper PHY interface implements the Gigabit Media Independent Interface (GMII) and the
Reduced Gigabit Media Independent Interface (RGMII) as defined in Version 1.2a of the
Hewlett-Packard* specification. RGMII has the benefit of reducing the PHY interface pin count
for high-port-count applications.
The fiber PHY interface implements an internal Serializer/Deserializer (SerDes) on each port to
allow direct connection to optical modules. The integration of the SerDes functionality reduces
PCB area requirements and system cost.
Product Features
4 Independent Ethernet MAC Ports which
support 3 interfaces for Copper or Fiber
Physical layer connectivity.
—IEEE 802.3 compliant
—RMON Statistics
—Independent Enable/Disable of any port
Copper Mode:
—RGMII for 10/100/1000 Mbps
connections
—GMII for 1000 Mbps full-duplex
connectivity
—IEEE 802.3 MDIO interface
Fiber Mode:
—Integrated SerDes interface for direct
connection to optical modules for
1000BASE-X connectivity
—Supports IEEE 802.3 fiber auto-
negotiation including forced mode
—Small Form Factor Pluggable (SFP)
Transceiver MSA compatible
System Packet Interface Level 3 (SPI3)
—Capable of data transfers at 4 Gbps in
both SPI3 modes:
32-bit Multi-PHY mode (133 Mhz)
4 x 8bit Single-PHY mode (125 Mhz)
Operating Temperature Ranges:
MIN MAX
Copper Mode: -40°C +85°C
Fiber Mode: 0°C +70°C
Flexible 32/16/8-bit CPU interface
Programmable Packet handling
—Filter packets with errors
—Filter broadcast, multicast, unicast and
VLAN packets
—Automatically pad transmitted packets
less than the minimum frame size
—Remove CRC from packets received
Performance Monitoring and Diagnostics
—CRC calculation and error detection
—Detection of length error, runt or overly
large packets
—Counters for dropped and errored
packets
—Loopback modes
—JTAG- and boundary-scan-capable
IEEE 802.3 Complaint Flow Control
—Loss-less flow control for up to 9.6 KB
packets and 5 km of fiber
—Jumbo frame support for 9.6 KB packets
Internal 32 KB receive FIFO and 10 KB
transmit FIFOs per channel
552-ball Ceramic Ball Grid Array (CBGA)
—1.8 V core, 2.5 V RGMII, GMII, OMI,
and 3.3 V SPI3 and CPU
—.18 µ CMOS process technology
Product Ordering Number:
HFIXF1104CE.B0 853714
Document Number: 278757
Revision Number: 007
Revision Date:
March 25, 2004