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Contents
Datasheet 7
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
9.2 Package Specifics for the IXF1104...................................................................................223
9.3 Package Information.........................................................................................................224
9.3.1 Example Package Marking..................................................................................226
10.0 Product Ordering Information..................................................................................................227
Figures
1 Block Diagram ............................................................................................................................20
2 Internal Architecture....................................................................................................................21
3Intel
®
IXF1104 552-Ball CBGA Assignments (Top View)...........................................................22
4 Interface Signals ........................................................................................................................37
5 Power Supply Sequencing..........................................................................................................62
6 Analog Power Supply Filter Network ..........................................................................................64
7 Packet Buffering FIFO ................................................................................................................70
8 Ethernet Frame Format ..............................................................................................................70
9 PAUSE Frame Format................................................................................................................71
10 Transmit Pause Control Interface...............................................................................................73
11 MPHY Transmit Logical Timing ..................................................................................................84
12 MPHY Receive Logical Timing ...................................................................................................85
13 MPHY 32-Bit Interface................................................................................................................85
14 SPHY Transmit Logical Timing...................................................................................................87
15 SPHY Receive Logical Timing....................................................................................................88
16 SPHY Connection for Two IXF1104 Ports (8-Bit Interface)........................................................89
17 MAC GMII Interconnect..............................................................................................................93
18 RGMII Interface ..........................................................................................................................95
19 TX_CTL Behavior .......................................................................................................................97
20 RX_CTL Behavior.......................................................................................................................97
21 Management Frame Structure (Single-Frame Format) ............................................................100
22 MDI State..................................................................................................................................101
23 SerDes Receiver Jitter Tolerance.............................................................................................105
24 I
2
C Random Read Transaction.................................................................................................110
25 Data Validity Timing..................................................................................................................112
26 Start and Stop Definition Timing...............................................................................................112
27 Acknowledge Timing.................................................................................................................113
28 Random Read...........................................................................................................................114
29 Mode 0 Timing..........................................................................................................................115
30 Mode 1 Timing..........................................................................................................................117
31 Read Timing Diagram - Asynchronous Interface......................................................................120
32 Write Timing Diagram - Asynchronous Interface......................................................................121
33 SPI3 Interface Loopback Path..................................................................................................125
34 Line Side Interface Loopback Path...........................................................................................126
35 SPI3 Receive Interface Timing.................................................................................................136
36 SPI3 Transmit Interface Timing................................................................................................138
37 RGMII Interface Timing.............................................................................................................140
38 1000BASE-T Transmit Interface Timing...................................................................................141
39 1000BASE-T Receive Interface Timing....................................................................................142
40 SerDes Timing Diagram ...........................................................................................................143
41 MDC High-Speed Operation Timing.........................................................................................144
42 MDC Low-Speed Operation Timing..........................................................................................144