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Datasheet 11
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
133 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................203
134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617).............................................204
135 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E)..............................................205
136 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ...................................206
137 TX FIFO Port Reset ($0x620)...................................................................................................206
138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624) ....................................207
139 TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629) ......................................208
140 TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630)...............................................209
141 TX FIFO Port Drop Enable ($0x63D)........................................................................................209
142 MDIO Single Command ($0x680).............................................................................................210
143 MDIO Single Read and Write Data ($0x681)............................................................................210
144 Autoscan PHY Address Enable ($0x682).................................................................................211
145 MDIO Control ($0x683).............................................................................................................211
146 SPI3 Transmit and Global Configuration ($0x700)...................................................................212
147 SPI3 Receive Configuration ($0x701) ......................................................................................214
148 Address Parity Error Packet Drop Counter ($0x70A) ...............................................................218
149 TX Driver Power Level Ports 0 - 3 ($0x784).............................................................................219
150 TX and RX Power-Down ($0x787) ...........................................................................................219
151 RX Signal Detect Level Ports 0 - 3 ($0x793) ............................................................................219
152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) ..............................................220
153 Optical Module Status Ports 0-3 ($0x799)................................................................................221
154 Optical Module Control Ports 0 - 3 ($0x79A) ............................................................................221
155 I
2
C Control Ports 0 - 3 ($0x79B)...............................................................................................222
156 I
2
C Data Ports 0 - 3 ($0x79F)...................................................................................................222
157 Product Information ..................................................................................................................227