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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
92 Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.2.3 Pre-Pending Function
The IXF1104 implements a pre-pending feature to allow 1518-byte Ethernet packets to be pre-
padded with two additional bytes of data so that the packet becomes low-word aligned. The 2-byte
pre-pend value is all zeros and is inserted before the destination address of the packet being pre-
pended. This value is fixed and cannot be changed.
This function is enabled by writing the appropriate data to the “RX FIFO Padding and CRC Strip
Enable ($0x5B3)" for each port.
A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional
bytes left over (1518/4 = 379.5). To eliminate the memory-management problems for a network
processor or switch fabric, the two remaining bytes are dealt with by the addition of two bytes to
the start of a packet. This results in a standard 1518-byte Ethernet packet received by the IXF1104
being forwarded to the higher-layer device as a 380-long-word packet. The upper-layer device is
responsible for stripping the additional two bytes.
This feature was added to the IXF1104 to assist in the design of higher-layer memory management.
The addition of the two extra bytes is not the default operation of the IXF1104 and must be enabled
by the user. The default operation of the IXF1104 SPI3 receive interface forwards data exactly as it
is received by the IXF1104 line interface.
5.3 Gigabit Media Independent Interface (GMII)
The IXF1104 supports a subset of the GMII interface standard as defined in IEEE 802.3 2000
Edition for 1 Gbps operation only. This subset is limited to operation at 1000 Mbps full-duplex.
The GMII Interface operates as a source synchronous interface only and does not accept a TXC
clock provided by a PHY device when operating at 10/100 Mbps speeds.
Note: The RGMII interface must be used for applications that require 10/100/1000 Mbps operation.
The IXF1104 does NOT support 10/100 Mbps copper PHY devices that are implemented using the
MII Interface.
Note: MII operation is not supported by the IXF1104.
The user can select GMII, RGMII, or Optical Module/SerDes functionality on a per-port basis.
This mode of operation is controlled through a configuration register.
While IEEE 802.3 specifies 3.3 V operation of GMII devices, most PHYs use 2.5 V signaling. The
IXF1104 provides a 2.5 V drive and is 3.3 V-tolerant on inputs.