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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Datasheet 105
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.6.2.6 Transmit Jitter
The SerDes core total transmit jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
• A deterministic component attributed to the SerDes core’s architectural characteristics
• A random component attributed to random thermal noise effects
Since the thermal noise component is random and statistical in nature, the SerDes core total
transmit jitter must be specified as a function of BER.
5.6.2.7 Receive Jitter
The SerDes core total receiver jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
• A deterministic component attributed to the SerDes core architectural characteristics
• A random component attributed to random thermal noise effects.
Figure 23. SerDes Receiver Jitter Tolerance
Note: UI = Unit interval.
B0745-02
10-1
0
10+1
10
0
10
1
10
2
10
3
10
4
10
5
10
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10
7
Frequency
Sinusoidal Jitter Mask
Peak-to-Peak Amplitude (UI)
16 ui
375 Hz 16 ui
22.5836 kHz 8.5 ui
1.9195 MHz 0.1 ui