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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
120 Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.9.1 Functional Description
5.9.1.1 Read Access
Read access involves the following:
• Detect assertion of asynchronous Read control signal and latch address
• Generate internal Read strobe
• Drive valid data onto processor bus
• Assert asynchronous Ready signal for required length of time
Figure 31 shows the timing of the asynchronous interface for Read access.
5.9.1.2 Write Access
Write process involves the following:
• Detect assertion of asynchronous Write control signal and latch address
• Detect de-assertion of asynchronous Write control signal and latch data
• Generate internal Write strobe
• Assert asynchronous Ready signal for required length of time
Figure 32 shows the timing of the asynchronous interface for Write accesses.
Figure 31. Read Timing Diagram - Asynchronous Interface
TCAS
TCAH
TCRR
TCDRS
TCDRH
TCDRD
TCRH
uPx_ADD[12:0]
uPx_RdN
uPx_CsN
uPx_Data[31:0]
uPx_RdyN