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Contents
8 Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
43 MDIO Write Timing Diagram ....................................................................................................145
44 MDIO Read Timing Diagram ....................................................................................................145
45 Bus Timing Diagram.................................................................................................................146
46 Write Cycle Diagram.................................................................................................................146
47 CPU Interface Read Cycle AC Timing......................................................................................148
48 CPU Interface Write Cycle AC Timing......................................................................................148
49 Pause Control Interface Timing................................................................................................150
50 JTAG AC Timing.......................................................................................................................151
51 System Reset AC Timing .........................................................................................................152
52 LED AC Interface Timing..........................................................................................................153
53 Memory Overview Diagram ......................................................................................................154
54 Register Overview Diagram......................................................................................................155
55 CBGA Package Diagram..........................................................................................................224
56 CBGA Package Side View Diagram.........................................................................................225
57 Intel
®
IXF1104 Example Package Marking ..............................................................................226
58 Ordering Information – Sample ................................................................................................227
Tables
1 Ball List in Alphanumeric Order by Signal Name........................................................................23
2 Ball List in Alphanumeric Order by Ball Location........................................................................29
3 SPI3 Interface Signal Descriptions.............................................................................................38
4 SerDes Interface Signal Descriptions.........................................................................................46
5 GMII Interface Signal Descriptions.............................................................................................47
6 RGMII Interface Signal Descriptions ..........................................................................................49
7 CPU Interface Signal Descriptions .............................................................................................50
9 Optical Module Interface Signal Descriptions.............................................................................52
8 Transmit Pause Control Interface Signal Descriptions ...............................................................52
10 MDIO Interface Signal Descriptions ...........................................................................................53
11 LED Interface Signal Descriptions..............................................................................................54
12 JTAG Interface Signal Descriptions............................................................................................54
13 System Interface Signal Descriptions.........................................................................................54
14 Power Supply Signal Descriptions..............................................................................................55
15 Ball Usage Summary..................................................................................................................56
16 Line Side Interface Multiplexed Balls..........................................................................................57
17 SPI3 MPHY/SPHY Interface.......................................................................................................58
18 Definition of Output and Bi-directional Balls During Hardware Reset.........................................60
19 Power Supply Sequencing .........................................................................................................63
20 Pull-Up/Pull-Down and Unused Ball Guidelines.........................................................................63
21 Analog Power Balls ....................................................................................................................64
22 CRC Errored Packets Drop Enable Behavior.............................................................................68
23 Valid Decodes for TXPAUSEADD[2:0].......................................................................................73
24 Operational Mode Configuration Registers ................................................................................75
25 RMON Additional Statistics ........................................................................................................80
26 GMII Interface Signal Definitions................................................................................................94
27 RGMII Signal Definitions ............................................................................................................96
28 TX_ER and RX_ER Coding Description.....................................................................................96
29 SerDes Driver TX Power Levels...............................................................................................103
30 IXF1104-to-SFP Optical Module Interface Connections...........................................................106
31 LED Interface Signal Descriptions............................................................................................115
32 Mode 0 Clock Cycle to Data Bit Relationship...........................................................................116