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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Datasheet 87
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.2.2.6 SPHY Logical Timing
SPI3 interface AC timing for SPHY can be found in Section 7.2, “SPI3 AC Timing Specifications”
on page 136. Logical timing in the following diagrams illustrates all signals associated with SPHY
mode. SPHY mode is similar to MPHY mode except the following signals are not used:
• TMOD[1:0]
• RMOD[1:0]
• TSX
• RSX
• Address Data appearing on the data bus
5.2.2.7 Transmit Timing (SPHY)
Packet transmission starts when TENB and TSOP indicate present data on the bus is the first word
in the packet. All subsequent clocks will contain valid data as long as TENB is active or until
TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed
when TENB is low.
5.2.2.8 Receive Timing (SPHY)
A packet is received when RSOP is asserted to indicate the data bus contains the first word of the
packet. All subsequent data is valid only while RVAL is high and until REOP is asserted. Receive
data can be temporarily halted when RENB is de-asserted and starts again on the second rising
edge of RFCLK following the assertion of RENB. When REOP is asserted RMOD indicates the
number of valid bytes in the last transfer.
Figure 14. SPHY Transmit Logical Timing
B3249-01
TFCLK
TENB
TSOP
TEOP
TERR
TDAT[7:0]_n
TPRTY
DTPA_n
B1 B2 B3 B60 B61 B62 B63 B64