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IXF1104 4-Port Gigabit Ethernet Media Access Controller
208 Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)
Name Description Address Type
*
Default
TX FIFO errored
frame drop counter
on Port 0
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
0x625 R 0x00000000
TX FIFO errored
frame drop counter
on Port 1
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
0x626 R 0x00000000
TX FIFO errored
frame drop counter
on Port 2
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
0x627 R 0x00000000
TX FIFO errored
frame drop counter
on Port 3
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
0x628 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write