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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Datasheet 67
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.1.1.3.2 Filter on Multicast Packet Match
This feature is enabled when bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any frame received in this mode that does not match the Port Multicast Address (reserved
multicast address recognized by MAC) is marked by the MAC to be dropped. The frame is dropped
if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in
“SPI3 Receive Configuration ($0x701)” on page 214).
When bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all multicast frames are
sent out the SPI3 interface.
5.1.1.3.3 Filter Broadcast Packets
This feature is enabled when bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is
dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1.
Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR
(see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all broadcast frames are
sent out the SPI3 interface.
5.1.1.3.4 Filter VLAN Packets
This feature is enabled when bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped
if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0
in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all VLAN frames are sent
out the SPI3 interface.
5.1.1.3.5 Filter Pause Packets
This feature is enabled when bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0.
Pause frames received in this mode are marked by the MAC to be dropped. The frame is dropped if
the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the
pause frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0
in “SPI3 Receive Configuration ($0x701)” on page 214).
When bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1, all pause frames are sent
out the SPI3 interface.
Note: Pause packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Index + 0x12)”.
5.1.1.3.6 Filter CRC Error Packets
This feature is enabled when bit 5 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0.
Frames received with an errored CRC are marked as bad frames and may optionally be dropped in
the RX FIFO. Otherwise, the frames are sent to the SPI3 interface and may be optionally signaled
with an RERR (see Table 22 “CRC Errored Packets Drop Enable Behavior” on page 68).