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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 21
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
Figure 2 illustrates the IXF1104 internal architecture.
Figure 2. Internal Architecture
SPI3 Interface
CPU Interface RMON Statistics
Packet
TX
Buffer
RX
Packet
Buffer
Packet
Buffer
Packet
Buffer
Clock Control Block Clock Register Block
PLLs
MDIO OMI
TX
TX
TX
RX
RX
RX
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
RGMII/GMII Interface
RGMII/GMII Interface
RGMII/GMII Interface
RGMII/GMII Interface
PMA Layer SerDes
PMA Layer SerDes
PMA Layer SerDes
PMA Layer SerDes
B3176-0
1