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IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller
Datasheet 79
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
5.1.7 Packet Buffer Dimensions
5.1.7.1 TX and RX FIFO Operation
5.1.7.1.1 TX FIFO
The IXF1104 TX FIFOs are implemented with 10 KB for each channel. This provides enough
space for at least one maximum size (10 KB) packet per-port storage and ensures that no under-run
conditions occur, assuming that the sending device can supply data at the required data rate.
A transfer to MAC Threshold parameter, which is user-programmable, determines when the FIFO
signals to the MAC that it has data to send. This is configured for specific block sizes, and the user
must ensure that an under-run does not occur. Also, the threshold can be set above the maximum
size of a normal Ethernet packet. This causes the FIFO to send only data to the MAC when this
threshold is exceeded or when the End-of-Packet marker is received. This second condition
eliminates the possibility of under-run, except when the controlling switch device fails. It can,
however, cause idle times on the media.
5.1.7.1.2 RX FIFO
The IXF1104 RX FIFOs are provisioned so that each port has its own 32 KB of memory space.
This is enough memory to ensure that there is never an over-run on any channel while transferring
normal Ethernet frame size data.
The FIFOs automatically generate Pause control frames to halt the link partner when the High
watermark is reached and to restart the link partner when the data stored in the FIFO falls below the
low-watermark. The RX and TX FIFOs have been sized to support lossless flow control with
9.6 KB packets. The RX FIFO has a programmable transfer threshold that sets the threshold at
which packets become “cut through” and starts transitioning to the SPI3 interface before the EOP
is received. Packets sizes below this threshold are treated as “store and forward.” Once a packet
size exceeds the RX FIFO transfer threshold, it can no longer be dropped by the RX FIFO even if it
is marked to be dropped by the MAC.
5.1.8 RMON Statistics Support
The IXF1104 supplies RMON statistics through the CPU interface. These statistics are available in
the form of counter values that can be accessed at specific addresses in the register maps (Table 59
through Table 69). Once read, these counters automatically reset and begin counting from zero. A
separate set of RMON statistics is available for each MAC device in the IXF1104.
Implementation of the RMON Statistics block is similar to the functionality provided by existing
Intel switch and router products. This implementation allows the IXF1104 to provide all of the
RMON Statistics group as defined by RFC2819. The IXF1104 supports the RMON RFC2819
Group 1 statistics counters. Table 25 notes the differences and additional statistics registers
supported by the IXF1104 that are outside the scope of the RMON RFC2819 document.