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The Status Byte Register
The Status Byte register group reports conditions from the other
register groups. Data in the instrument’s output buffer is immediately
reported on the “Message Available” bit (bit 4). Clearing an event
register from one of the other register groups will clear the corresponding
bits in the Status Byte condition register. Reading all messages from the
output buffer, including any pending queries, will clear the “Message
Available” bit. To set the enable register mask and generate an
SRQ
(service request), you must write a decimal value to the register using
the *SRE command.
Bit Definitions – Status Byte Register
The Status Byte condition register is cleared when:
• You execute the *CLS (clear status) command.
• You read the event register from one of the other register groups (only the
corresponding bits are cleared in the Status Byte condition register).
The Status Byte enable register is cleared when:
• You execute the *SRE 0 command.
• You turn the power on and have previously configured the
instrument to clear the enable register using the *PSC 1 command.
Note that the enable register will not be cleared at power-on if you
have configured the instrument using the *PSC 0 command.
Bit Number
Decimal
Value Definition
0 Not Used
1 Alarm Condition
2 Not Used
3 Questionable Data
4 Message Available
5 Standard Event
6 Master Summary
7 Standard Operation
1
2
4
8
16
32
64
128
Returns “0”.
One or more bits are set in the Alarm Register
(bits must be enabled).
Returns “0”.
One or more bits are set in the Questionable
Data Register (bits must be enabled).
Data is available in the instrument’s output buffer.
One or more bits are set in the Standard Event
Register (bits must be enabled).
One or more bits are set in the Status Byte
Register (bits must be enabled).
One or more bits are set in the Standard
Operation Register (bits must be enabled).
5
Chapter 5 Remote Interface Reference
The SCPI Status System
277