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Using the Message Available Bit (MAV)
You can use the Status Byte “Message Available” bit (bit 4) to determine
when data is available to read into your computer. The instrument
subsequently clears bit 4 only after all messages have been read from
the output buffer.
To Interrupt Your Bus Controller Using SRQ
1. Send a Device Clear message to clear the instrument’s output buffer
(e.g., CLEAR 709).
2. Clear the event registers using the *CLS command.
3. Set up the enable register masks. Execute the *ESE command to
configure the Standard Event enable register and the *SRE command
to configure the Status Byte enable register.
4. Send the *OPC? command and enter the result to ensure synchronization.
5. Enable your computer’s
IEEE-488 SRQ interrupt.
To Determine When a Command Sequence is Completed
1. Send a Device Clear message to clear the instrument’s output buffer
(e.g., CLEAR 709).
2. Clear the event registers using the *CLS command.
3. Enable the “Operation Complete” bit (bit 0) in the Standard Event
register using the *ESE 1 command.
4. Send the *OPC? command and enter the result to ensure synchronization.
5. Execute your command string to program the desired configuration,
and then send the *OPC command as the last command (note that if a
scan is in progress, the *OPC command will wait until the entire
scan is complete). When the command sequence is completed, the
“Operation Complete” bit (bit 0) is set in the Standard Event register.
6. Use a Serial Poll to check to see when bit 5 (routed from the Standard
Event register) is set in the Status Byte condition register. You could
also configure the instrument for an
SRQ interrupt by sending
*SRE 32 (Status Byte enable register, bit 5).
5
Chapter 5 Remote Interface Reference
The SCPI Status System
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