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LIST OF FIGURES (2/9)
Figure No. Title Page
7-1 Block Diagram of Clock Generator ............................................................................................ 166
7-2 Subsystem Clock Feedback Resistor ........................................................................................ 167
7-3 Processor Clock Control Register Format ................................................................................. 168
7-4 Oscillation Mode Selection Register Format ............................................................................. 170
7-5 Main System Clock Waveform due to Writing to OSMS .......................................................... 170
7-6 External Circuit of Main System Clock Oscillator ..................................................................... 171
7-7 External Circuit of Subsystem Clock Oscillator......................................................................... 172
7-8 Examples of Oscillator with Bad Connection ............................................................................ 172
7-9 Main System Clock Stop Function ............................................................................................. 176
7-10 System Clock and CPU Clock Switching .................................................................................. 179
8-1 16-Bit Timer/Event Counter Block Diagram .............................................................................. 186
8-2 16-Bit Timer/Event Counter Output Control Circuit Block Diagram ......................................... 187
8-3 Timer Clock Selection Register 0 Format ................................................................................. 191
8-4 16-Bit Timer Mode Control Register Format ............................................................................. 192
8-5 Capture/Compare Control Register 0 Format ........................................................................... 193
8-6 16-Bit Timer Output Control Register Format ........................................................................... 194
8-7 Port Mode Register 3 Format..................................................................................................... 195
8-8 External Interrupt Mode Register 0 Format............................................................................... 196
8-9 Sampling Clock Select Register Format.................................................................................... 197
8-10 Control Register Settings for Interval Timer Operation ............................................................ 198
8-11 Interval Timer Configuration Diagram........................................................................................ 199
8-12 Interval Timer Operation Timings .............................................................................................. 199
8-13 Control Register Settings for PWM Output Operation .............................................................. 201
8-14 Example of D/A Converter Configuration with PWM Output .................................................... 202
8-15 TV Tuner Application Circuit Example....................................................................................... 202
8-16 Control Register Settings for PPG Output Operation ............................................................... 203
8-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ......................................................................................................... 204
8-18 Configuration Diagram for Pulse Width Measurement by Free-Running Counter .................. 205
8-19 Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ................................................................. 205
8-20 Control Register Settings for Two Pulse Width Measurements with
Free-Running Counter ................................................................................................................ 206
8-21 Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ....................................................................................................... 207
8-22 Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ............................................................................................................... 208
8-23 Timing of Pulse Width Measurement Operation by Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)............................................................... 209
8-24 Control Register Settings for Pulse Width Measurement by Means of Restart ...................... 210
8-25 Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ...................................................................................................... 210