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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
(2) In I
2
C bus mode
The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of interrupt timing specify register (SINT).
<1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is
enabled). Set 1 to the P27 output latch. While serial transfer is suspended, SCL is set to 0.
<2> Manipulate the content of the CLC bit of SINT by executing the bit manipulation instruction.
Figure 18-28. SCK0/SCL/P27 Pin Configuration
Note The level of SCL signal follows the contents of logic circuit shown in Figure 18-29.
Figure 18-29. Logic Circuit of SCL Signal
Remarks 1. This figure shows the relationship of each signal, and does not show the internal circuit.
2. CLC: Bit 3 of interrupt timing specify register (SINT)
To Internal
Circuit
SCK0/SCL/P27
P27 Output
Latch
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
SCL
From Serial Clock
Control Circuit
Set 1
Note
SCL
CLC (Set by bit manipulation instruction)
Serial Clock
(low level when transfer stops)
Wait Request Signal