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CHAPTER 28 INSTRUCTION SET
Instruction Mnemonic Operands Byte Clock Operation Flag
Group
Note 1 Note 2
ZACCY
Call / CALL !addr16 3 7 —
(SP – 1) ← (PC + 3)H, (SP - 2) ← (PC + 3)L,
return PC ← addr16, SP ← SP – 2
CALLF !addr11 2 5 —
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PC15 - 11 ← 00001, PC10 - 0 ← addr11,
SP ← SP – 2
CALLT [addr5] 1 6 —
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
BRK 1 6 — (SP – 1) ← PSW, (SP – 2) ← (PC + 1)H,
(SP – 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP – 3, IE ← 0
RET 1 6 — PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 1 6 — PCH ← (SP + 1), PCL ← (SP), R R R
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
RETB 1 6 — PCH ← (SP + 1), PCL ← (SP), R R R
PSW ← (SP + 2), SP ← SP + 3
Stack PUSH PSW 1 2 — (SP – 1) ← PSW, SP ← SP – 1
manipulate rp 1 4 — (SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
POP PSW 1 2 — PSW ← (SP), SP ← SP + 1 R R R
rp 1 4 — rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
MOVW SP, #word 4 — 10 SP ← word
SP, AX 2 — 8 SP ← AX
AX, SP 2 — 8 AX ← SP
Uncondi- BR !addr16 3 6 — PC ← addr16
tional $addr16 2 6 — PC ← PC + 2 + jdisp8
branch AX 2 8 — PCH ← A, PCL ← X
Conditional
BC $addr16 2 6 — PC ← PC + 2 + jdisp8 if CY = 1
branch BNC $addr16 2 6 — PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 — PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 — PC ← PC + 2 + jdisp8 if Z = 0
Notes 1. For instructions that access the internal high-speed RAM area or perform no data access
2. For instructions that access an area other than the internal high-speed RAM area
Remarks 1. One clock in the “Clock” columns is equal to one cycle of the CPU clock (f
CPU) selected by the processor
clock control register (PCC).
2. The values in the “Clock” column assumes that the internal ROM area contains programs.