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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI1 input cycle 2
8
x TI1 input cycle TI1 input edge cycle
0001 TI1 input cycle 2
8
x TI1 input cycle TI1 input edge cycle
2 x 1/fX 2
2
x 1/fX 2
9
x 1/fX 2
10
x 1/fX 2 x 1/fX 2
2
x 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
2
2
x 1/fX 2
3
x 1/fX 2
10
x 1/fX 2
11
x 1/fX 2
2
x 1/fX 2
3
x 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
2
3
x 1/fX 2
4
x 1/fX 2
11
x 1/fX 2
12
x 1/fX 2
3
x 1/fX 2
4
x 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
2
4
x 1/fX 2
5
x 1/fX 2
12
x 1/fX 2
13
x 1/fX 2
4
x 1/fX 2
5
x 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
2
5
x 1/fX 2
6
x 1/fX 2
13
x 1/fX 2
14
x 1/fX 2
5
x 1/fX 2
6
x 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
2
6
x 1/fX 2
7
x 1/fX 2
14
x 1/fX 2
15
x 1/fX 2
6
x 1/fX 2
7
x 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
2
7
x 1/fX 2
8
x 1/fX 2
15
x 1/fX 2
16
x 1/fX 2
7
x 1/fX 2
8
x 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
2
8
x 1/fX 2
9
x 1/fX 2
16
x 1/fX 2
17
x 1/fX 2
8
x 1/fX 2
9
x 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
2
9
x 1/fX 2
10
x 1/fX 2
17
x 1/fX 2
18
x 1/fX 2
9
x 1/fX 2
10
x 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
2
11
x 1/fX 2
12
x 1/fX 2
19
x 1/fX 2
20
x 1/fX 2
11
x 1/fX 2
12
x 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. f
X : Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode selection register (OSMS)
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)
4. Figures in parentheses apply to operation with f
X = 5.0 MHz.
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL13 TCL12 TCL11 TCL10