Filter
Top Products
387
CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
<6> <5> <4> <3> <2> <1> <0><7>
Symbol
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT
When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Address After Reset R/W
CMDT
When CMDT = 1, SO0 Iatch is cleared to 0. After SO0 latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Set bits 0 to 3 to 0 when the 2-wire serial I/O mode is selected.
Remark CSIIF0 : Interrupt request flag corresponding to INTCSI0
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
<6> <5> <4> <3> <2> 1 07
Symbol
SINT 0 CLD SIC CLC WREL WAT1 WAT0
FF63H 00H R/W
Note 1
Address After Reset R/W
SVAM
SIC
0
INTCSI0 Interrupt Factor Selection
CSIIF0 is set upon termination of serial interface channel 0 transfer
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
CLD
0
1
SCK0 Pin Level
Note 2
Low level
High level
R/W
R
1