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CHAPTER 22 INTERRUPT FUNCTIONS
22.4.5 Interrupt request reserve
Some instructions may reserve the acknowledge of an instruction request until the completion of the execution
of the next instruction even if the interupt request is generated during the execution. The following shows such
instructions (interrupt request reserve instruction).
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1/CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
•EI
•DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1
registers
Caution BRK instruction is not an interrupt request reserve instruction described above. However, in
a software interrupt started by the execution of BRK instruction, the IE flag is cleared to 0.
Therefore, interrupt requests are not acknowledged even when a maskable interrupt request
is issued during the execution of the BRK instruction. However, non-maskable interrupt
requests are acknowledged.
Figure 22-17 shows the interrupt request hold timing.
Figure 22-17. Interrupt Request Hold
Remarks 1. Instruction N: Instruction that holds interrupts requests
2. Instruction M: Instructions other than interrupt request pending instruction
3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
CPU processing
xxIF
Instruction N Instruction M
Save PSW and PC,
Jump to interrupt service
Interrupt service
program