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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
Figure 18-5. Serial Bus Interface Control Register Format (2/2)
Notes 1. Setting should be performed before transfer.
2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output
using ACKT.
3. The busy mode can be canceled by start of serial interface transfer or reception of address
signal. However, the BSYE flag is not cleared to 0.
4. When using the wake-up function, set BSYE to 1.
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
ACKE Acknowledge Signal Output Control
0
Disables acknowledge signal automatic output. (However, output with ACKT is enabled)
Used for reception when 8-clock wait mode is selected or for transmission.
Note 2
Enables acknowledge signal automatic output.
Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Used in reception with 9-clock wait mode selected.
1
R/W
R
ACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
• While executing the transfer start instruction
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCL clock after completion of
transfer
BSYE Control of N-ch Open-Drain Output for Transmission in I
2
C Bus Mode
0
Output enabled (transmission)
R/W
Note 3
1
Note 4
Output disabled (reception)
Note 1