Filter
Top Products
585
CHAPTER 28 INSTRUCTION SET
Instruction Mnemonic Operands Byte Clock Operation Flag
Group
Note 1 Note 2
ZACCY
16-bit data MOVW rp, #word 3 6 — rp ← word
transfer saddrp, #word 4 8 10 (saddrp) ← word
sfrp, #word 4 — 10 sfrp ← word
AX, saddrp 2 6 8 AX ← (saddrp)
saddrp, AX 2 6 8 (saddrp) ← AX
AX, sfrp 2 — 8 AX ← sfrp
sfrp, AX 2 — 8 sfrp ← AX
AX, rp
Note 3
1 4 — AX ← rp
rp, AX
Note 3
1 4 — rp ← AX
AX, !addr16 3 10 12 + 2n AX ← (addr16)
!addr16, AX 3 10 12 + 2m (addr16) ← AX
XCHW AX, rp
Note 3
1 4 — AX ↔ rp
8-bit ADD A, #byte 2 4 — A, CY ← A + byte x x x
operation saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte x x x
A, r
Note 4
2 4 — A, CY ← A + r x x x
r, A 2 4 — r, CY ← r + A x x x
A, saddr 2 4 5 A, CY ← A + (saddr) x x x
A, !addr16 3 8 9 + n A, CY ← A + (addr16) x x x
A, [HL] 1 4 5 + n A, CY ← A + (HL) x x x
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) x x x
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) x x x
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) x x x
ADDC A, #byte 2 4 — A, CY ← A + byte + CY x x x
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY x x x
A, r
Note 4
2 4 — A, CY ← A + r + CY x x x
r, A 2 4 — r, CY ← r + A + CY x x x
A, saddr 2 4 5 A, CY ← A + (saddr) + CY x x x
A, !addr16 3 8 9 + n A, CY ← A + (addr16) + CY x x x
A, [HL] 1 4 5 + n A, CY ← A + (HL) + CY x x x
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) + CY x x x
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) + CY x x x
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) + CY x x x
Notes 1. For instructions that access the internal high-speed RAM area or perform no data access
2. For instructions that access an area other than the internal high-speed RAM area
3. Only when rp = BC, DE, or HL
4. Except when “r = A”
Remarks 1. One clock in the “Clock” columns is equal to one cycle of the CPU clock (f
CPU) selected by the processor
clock control register (PCC).
2. The values in the “Clock” column assumes that the internal ROM area contains programs.
3. n indicates wait cycles to be inserted when an external expansion memory area is read from.
4. m indicates wait cycles to be inserted when an external expansion memory area is written to.