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CHAPTER 20 SERIAL INTERFACE CHANNEL 2
(3) UART mode cautions
(a) When transmit operation is stopped by clearing (0) bit 7 (TXE) of the asynchronous serial interface mode
register (ASIM) during transmission, be sure to set the transmit shift register (TXS) to FFH, then set
the TXE to 1, before executing the next transmission.
(b) When receive operation is stopped by clearing (0) bit 6 (RXE) of the asynchronous serial interface mode
register (ASIM) during reception, the state of the receive buffer register (RXB) and whether a receive
completion interrupt request (INTSR) is generated or not differ depending on the receive stop timing.
Figure 20-11 shows the timing.
Figure 20-11. State of Receive Buffer Register (RXB) When Receive Operation is Stopped and
Whether Interrupt Request (INTSR) is Generated or Not
When RXE is set to 0 at a time indicated by
<
1
>
, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by
<
2
>
, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by
<
3
>
, RXB renews the data and generates INTSR.
ParityRxD Pin
RXB
INTSR
<
3
><
1
>
<
2
>