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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception
(shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial
operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
Note that, if a bus is driven in the I
2
C bus mode or 2-wire serial I/O mode, the bus pin must serve for both
input and output. Therefore, the transmission N-ch open-drain output of the device which will start reception
of data must be set to high-impedance state beforehand. Consequently, write FFH to SIO0 in advance.
In the I
2
C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC)
set to 0.
RESET input makes SIO0 undefined.
Caution In the I
2
C bus mode, do not execute write instructions to SI0 while WUP (bit 5 of serial
operation mode register 0 (CSIM0)) = 1. Data can be received when using the wake-up
function (WUP = 1) even if write instruction to SIO0 is not executed. For the wake-up
function, refer to 18.4.4 (1) (c) Wake-up function.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial
I/O mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI)
of serial operating mode register 0 (CSIM0) becomes 1.
Address of the data of LSB-masked high-order 7 bits can be compared by setting bit 4 (SVAM) of the interrupt
timing specify register (SINT).
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0. In the I
2
C bus mode, when bit 5 (WUP) of CSIM0 is set (1), the wake-up function can be
used. In this case, the interrupt request signal (INTCSI0) is generated if the slave address output from the
master and the SVA value match (the interrupt request signal is generated also when a stop condition is
detected). This interrupt request enables to recognize the generation of the communication request from
the master device. Set SIC to 1 when using the wake-up function.
Further, when SVA transmits data as master or slave device in the the I
2
C bus mode or 2-wire serial I/O
mode, errors are detected if any.
RESET input makes SVA undefined.
(3) SO0 latch
This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by
software.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check
whether 8-bit data has been transmitted/received.
(5) Serial clock control circuit
This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system
clock is used, the circuit also controls clock output to the SCK0/SCL/P27 pin.