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1.1 LSI53C810A System Diagram 1-7
1.2 LSI53C810A Chip Block Diagram 1-8
2.1 DMA FIFO Sections 2-8
2.2 LSI53C810A Host Interface Data Paths 2-10
2.3 Active or Regulated Termination 2-12
2.4 Determining the Synchronous Transfer Rate 2-15
4.1 LSI53C810A Pin Diagram 4-2
4.2 Functional Signal Grouping 4-4
5.1 Register Address Map 5-2
6.1 SCRIPTS Overview 6-5
6.2 Block Move Instruction Register 6-8
6.3 I/O Instruction Register 6-16
6.4 Read/Write Register Instruction 6-25
6.5 Transfer Control Instruction 6-30
6.6 Memory to Memory Move Instruction 6-37
6.7 Load and Store Instruction Format 6-42
7.1 Rise and Fall Time Test Conditions 7-8
7.2 SCSI Input Filtering 7-8
7.3 Hysteresis of SCSI Receiver 7-8
7.4 Input Current as a Function of Input Voltage 7-9
7.5 Output Current as a Function of Output Voltage 7-9
7.6 Clock Timing 7-10
7.7 Reset Input 7-11
7.8 Interrupt Output Waveforms 7-11
7.9 PCI Configuration Register Read 7-13
7.10 PCI Configuration Register Write 7-14
7.11 Target Read 7-15
7.12 Target Write 7-16
7.13 OpCode Fetch, Nonburst 7-17
7.14 Burst Opcode Fetch 7-18
7.15 Back-to-Back Read 7-19
7.16 Back-to-Back Write 7-20
7.17 Burst Read 7-22
7.18 Burst Write 7-24
7.19 Initiator Asynchronous Send 7-27
7.20 Initiator Asynchronous Receive 7-28